1. Field of the Invention
The present invention relates to a method of exposing a layer with a light and a method of manufacturing a thin film transistor substrate for a liquid crystal display device using the same. More particularly, the present invention relates to a method of exposing a layer with a light that reduces defects caused by a misalignment during the exposure process, and a method of manufacturing a thin film transistor substrate for a liquid crystal display device using the same.
2. Description of the Related Art
Generally, display devices are electric optical devices converting electrical signals into visual signals that provide information. A liquid crystal display device includes upper and lower substrates, and a liquid crystal layer interposed between the upper and lower substrates. The upper substrate includes common electrodes and color filters. The lower substrate includes thin film transistors and pixel electrodes. In the liquid crystal display device, electric fields formed between the electrodes on the upper and lower substrates adjust the arrangements of liquid crystal molecules to control the quantity of light that passes through the liquid crystal layer.
The liquid crystal display device has been used for information display terminals such as a viewfinder of a video camera, a color television set, a high definition projection-type television, a personal computer, a word processor, a computer monitor, etc. Particularly, an active matrix type twisted nematic (TN) mode liquid crystal display device adopts thin film transistors as a switching device. Thus, high contrast can be maintained even when an image requiring high capacity is displayed.
In the active matrix type liquid crystal display device, the switching devices such as the thin film transistors are formed on the pixel electrodes arranged in a matrix form. Electrical signals are provided to each of the pixel electrodes through the switching devices to control the optical characteristics of the liquid crystal.
The liquid crystal display device includes a thin film transistor substrate (or array substrate) having the switching devices.
The thin film transistor substrate also has gate lines electrically connected to gate electrodes of the thin film transistors, data lines electrically connected to data (source) electrodes, gate pads transmitting signals from outside to the gate lines, and data pads transmitting signals from outside to the data lines. A pixel region that is defined by crossing of the gate line and the data line has a pixel electrode that is electrically connected to a drain electrode of the thin film transistor.
When the liquid crystal display device is operated, positive voltage and negative voltage are alternately applied to the data lines, and the voltage of the pixel electrodes varies in accordance with the voltage applied to the data lines.
The gate lines, data lines and pixel electrodes are formed on the thin film transistor substrate by photolithography processes. A stepper type exposure process or an aligner type exposure process may be performed as an exposure process. In stepper type exposure process, the thin film transistor is formed into a plurality of virtual blocks (or cells), and each of the blocks is exposed in sequence. In aligner process, the thin film transistor is exposed at once.
A general exposure process using a Canon exposure system will be briefly described.
FIG. 1A is a schematic perspective view illustrating a general optical exposure system.
Referring to FIG. 1A, the optical exposure system includes a mask 10 having patterns to be projected on a substrate, a light source 20 having a slit and a bent shape, a large mirror 30, a concave mirror 40, a convex mirror 50 and a plate 60 on which the substrate is to be mounted.
A light generated from the light source 20 passes through the mask 10 while the light source 20 is moved in a direction of scanning. The light passes through the large mirror 30, the concave mirror 40 and the convex mirror 50 in sequence to transcribe patterns of the mask 10 at the substrate.
FIG. 1B is a plan view illustrating an arrangement of the plate and the mask of FIG. 1A.
Referring to FIG. 1B, through the mask 10 in which two cells are arranged, the light source 20 projects the patterns of the mask to the cells with bent shape scanning. The improvement of process yield can be achieved by arranging as many cells as possible in a mask.
Generally, a misalignment occurs during the exposure process, even for an accurate exposure system. In particular, when the pixel electrode and the data line are formed on different layers, the interval between the pixel electrode and the data line may be deviated from a designed value due to separate exposure processes. Thus, a coupling capacitance between the data line and the pixel electrode through the insulation layer becomes different from the designed value. In addition, the interval between the pixel electrode and the data line becomes irregular. Thus, even when substantially same gray scale voltage is applied to the pixel electrode, the interval between the pixel electrode and the data line varies.
When a stepper is used as the exposure system, one display region is divided into several blocks and then each of the blocks is exposed in sequence. Thus, each block may have a different size of interval between the data line and the pixel electrode one another. Thus, the light that passes though each block has different luminance resulting in stitch defect with chessboard pattern.
When an aligner is used as the exposure system, a misalignment between layers occurs to cause defects of the display device. These defects of the display device are observed as vertical lines and called as vertical line shaped blot.
FIGS. 2A and 2B are plan views illustrating pattern size variations caused by a misalignment between a data line and a pixel electrode in a cell. In FIG. 2A, twelve measuring points are shown for example, and in FIG. 2B, pattern sizes corresponding to each measuring point of FIG. 2A are shown.
Referring to FIGS. 2A and 2B, the size of the intervals between the data line and the pixel electrode may be varied according to the measuring points. These differences in intervals cause the difference in coupling capacitance between the data line and the pixel electrode to show the vertical line shaped blot and variations in luminance.
One of the methods for reducing variation ranges of the coupling capacitance is amending the coordinates of the exposure system in consideration of the size of the intervals between the pixel electrode and the data line, which is formed already. In practice, the intervals between the pixel electrode and the data line are controlled within allowable values using the method explained above.
Korean Patent Laid Open publication No. 1999-81025 discloses a method of detecting intervals between a pixel electrode and a data line
Korean Patent Laid Open Publication No. 1999-41951 discloses a method of forming a source electrode and a pixel electrode together to reduce the difference in coupling capacitance between the data line and pixel electrode caused by the misalignment during the exposure process using stepper.
Recently, as the substrate becomes larger, a cell corresponding to the maximum exposure area of the mask is exposed during the exposure process. Currently, there is no solution for the problems of the vertical line caused by the misalignment of layers in the cell. Thus, as the glass substrate becomes larger, the misalignment of layers induces lowering of productivity.